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A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM–PM Distortion Self-Compensation

Park, J. S. et al.

IEEE journal of solid-state circuits. VOL 53; NUMBER 2, ; 2018, 340-356 -- IEEE; 1998

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A 0.3-V CMOS Biofuel-Cell-Powered Wireless Glucose/Lactate Biosensing System

Yeknami, A. F. et al.

IEEE journal of solid-state circuits. VOL 53; NUMBER 11, ; 2018, 3126-3139 -- IEEE; 1998

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Sub- $\mu$ Vrms-Noise Sub- $\mu$ W/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging

Kim, C. et al.

IEEE journal of solid-state circuits. VOL 53; NUMBER 11, ; 2018, 3101-3110 -- IEEE; 1998

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A Multimodal CMOS MEA for High-Throughput Intracellular Action Potential Measurements and Impedance Spectroscopy in Drug-Screening Applications

Lopez, C. M. et al.

IEEE journal of solid-state circuits. VOL 53; NUMBER 11, ; 2018, 3076-3086 -- IEEE; 1998

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A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

Sinangil, M. E. et al.

IEEE journal of solid-state circuits. VOL 51; NUMBER 2, ; 2016, 557-567 -- IEEE; 1998 Part 2; (pages 557-567) -- 2016

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A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

Wang, J. S. et al.

IEEE journal of solid-state circuits. VOL 50; NUMBER 11, ; 2015, 2635-2644 -- IEEE; 1998 Part 11; (pages 2635-2644) -- 2015

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A Multi-Phase Sub-Harmonic Injection Locking Technique for Bandwidth Extension in Silicon-Based THz Signal Generation

Chi, T. et al.

IEEE journal of solid-state circuits. VOL 50; NUMBER 8, ; 2015, 1861-1873 -- IEEE; 1998 Part 8; (pages 1861-1873) -- 2015

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Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS

Hu, S. et al.

IEEE journal of solid-state circuits. VOL 50; NUMBER 5, ; 2015, 1094-1106 -- IEEE; 1998 Part 5; (pages 1094-1106) -- 2015

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A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics

Tsai, J. H. et al.

IEEE journal of solid-state circuits. VOL 50; NUMBER 11, ; 2015, 2533-2548 -- IEEE; 1998 Part 11; (pages 2533-2548) -- 2015

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Post-Si Programmable ESD Protection Circuit Design: Mechanisms and Analysis

Wang, X. et al.

IEEE journal of solid-state circuits. VOL 48; NUMBER 5, ; 2013, 1237-1249 -- IEEE; 1998 Part 5; (pages 1237-1249) -- 2013

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  1. Wang, A. Z. H.
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