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Refined by: journal title: IEEE journal of solid-state circuits. remove subject: ISSCC remove
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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

Gupta, S. K.; Inerfield, M. A.; Wang, J.

IEEE journal of solid-state circuits.; IEEE International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2006, 2650-2657 -- IEEE; 2006 (pages 2650-2657) -- 2006

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A 28 nm 0.6 V Low Power DSP for Mobile Applications

Ickes, N. et al.

IEEE journal of solid-state circuits.; Solid-state circuits; San Francisco, CA, 2011; Feb, 2012, 35-46 -- Institute of Electrical and Electronics Engineers; 2012 Part: Part 1; (pages 35-46) -- 2012

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A 0.1-mum 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

Kang, S. et al.

IEEE journal of solid-state circuits.; International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2007, 210-218 -- IEEE,; 2007 Part: Part 1; (pages 210-218) -- 2007

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A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

Lee, K.-J. et al.

IEEE journal of solid-state circuits.; IEEE international solid state circits conference (ISSCC); San Francisco, CA, 2007; Feb, 2008, 150-162 -- IEEE; 2008 (pages 150-162) -- 2008

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5
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A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

Lin, C.-C. et al.

IEEE journal of solid-state circuits.; International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2007, 170-182 -- IEEE,; 2007 Part: Part 1; (pages 170-182) -- 2007

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A 125 muW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications

Liu, T.-M. et al.

IEEE journal of solid-state circuits.; International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2007, 161-169 -- IEEE,; 2007 Part: Part 1; (pages 161-169) -- 2007

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A 4-MB On-Chip L2 Cache for a 90-nm 1.6-GHz 64-bit Microprocessor

McIntyre, H. et al.

IEEE journal of solid-state circuits.; IEEE international solid-state circuits conference; IEEE 2004 ISSCC, digital, technology directions, memory and signal processing; , 2004; Feb, 2005, 52-59 -- IEEE Solid-State Circuits Society,; 2005 Part: Part 1; (pages 52-59) -- 2005

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by this Author/Contributor:

  1. Cho, B.‐H.
  2. Lee, K.‐J.
  3. Cho, W. Y.
  4. Kim, H. J.
  5. Choi, B. G.

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