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Results 1 - 10 of 13  for Everything in this catalogue

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A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

Lin, C.-C. et al.

IEEE journal of solid-state circuits.; International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2007, 170-182 -- IEEE,; 2007 Part: Part 1; (pages 170-182) -- 2007

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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

Gupta, S. K.; Inerfield, M. A.; Wang, J.

IEEE journal of solid-state circuits.; IEEE International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2006, 2650-2657 -- IEEE; 2006 (pages 2650-2657) -- 2006

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An 87GHz QPSK Transceiver with Costas-Loop Carrier Recovery in 65nm CMOS

Huang, S.-J.|Yeh, Y.-C.|Wang, H.|Chen, P.-N.|Lee, J.

Piscataway, N.J.; IEEE; 2011 (pages 168-169)

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A 4-MB On-Chip L2 Cache for a 90-nm 1.6-GHz 64-bit Microprocessor

McIntyre, H. et al.

IEEE journal of solid-state circuits.; IEEE international solid-state circuits conference; IEEE 2004 ISSCC, digital, technology directions, memory and signal processing; , 2004; Feb, 2005, 52-59 -- IEEE Solid-State Circuits Society,; 2005 Part: Part 1; (pages 52-59) -- 2005

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A Low-Overhead Self-Healing Embedded System for Ensuring High Yield and Long-Term Sustainability of 60GHz 4Gb/s Radio-on-a-Chip

Tang, A. et al.

Digest of technical papers / IEEE International Solid-State Circuits Conference.; 2012 IEEE international solid-state circuits conference digest of technical papers: (ISSCC 2012), San Francisco, California, USA, 19-23 February 2012; San Francisco, CA, 2012; Feb, 2012, 316-317 -- Piscataway, NJ; IEEE; 2012 Part: Part 2012; (pages 316-317) -- 2012

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Zero-Order Control of Boost DC-DC Converter with Transient Enhancement Using Residual Current

Kong, T.-H.|Woo, Y.-J.|Wang, S.-W.|Hong, S.-W.|Cho, G.-H.

Piscataway, N.J.; IEEE; 2011 (pages 390-391)

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A 40mV Transformer-Reuse Self-Startup Boost Converter with MPPT Control for Thermoelectric Energy Harvesting

Im, J.-P. et al.

Digest of technical papers / IEEE International Solid-State Circuits Conference.; 2012 IEEE international solid-state circuits conference digest of technical papers: (ISSCC 2012), San Francisco, California, USA, 19-23 February 2012; San Francisco, CA, 2012; Feb, 2012, 104-105 -- Piscataway, NJ; IEEE; 2012 Part: Part 2012; (pages 104-105) -- 2012

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A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

Lee, K.-J. et al.

IEEE journal of solid-state circuits.; IEEE international solid state circits conference (ISSCC); San Francisco, CA, 2007; Feb, 2008, 150-162 -- IEEE; 2008 (pages 150-162) -- 2008

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A 0.1-mum 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

Kang, S. et al.

IEEE journal of solid-state circuits.; International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2007, 210-218 -- IEEE,; 2007 Part: Part 1; (pages 210-218) -- 2007

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A 56GS/s 6b DAC in 65nm CMOS with 256x6b Memory

Greshishchev, Y.M.|Pollex, D.|Wang, S.-C.|Besson, M.|Flemeke, P.|Szilagyi, S.|Aguirre, J.|Falt, C.|Ben-Hamida, N.|Gibbins, R.

Piscataway, N.J.; IEEE; 2011 (pages 194-195)

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by this Author/Contributor:

  1. Wang, A
  2. Ickes, N.
  3. Woo, Y. J.
  4. Mair, H.
  5. Gu, J.

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