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Results 1 - 10 of 48  for Everything in this catalogue

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Refined by: journal title: IEEE journal of solid-state circuits. remove creation date: 2004To2007 remove
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A Low-Power Half-Delay-Line Fast Skew-Compensation Circuit

Wang, Y.-M.; Wang, J.-S.

IEEE journal of solid-state circuits. VOL 39; PART 6, ; 2004, 906-918 -- IEEE; 1998 (pages 906-918) -- 2004

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The CMOS Carry-Forward Adders

Huang, C.-H. et al.

IEEE journal of solid-state circuits. VOL 39; PART 2, ; 2004, 327-336 -- IEEE; 1998 (pages 327-336) -- 2004

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An AND-Type Match-Line Scheme for High-Performance Energy-Efficient Content Addressable Memories

Li, H.-Y. et al.

IEEE journal of solid-state circuits. VOL 41; NUMB 5, ; 2006, 1108-1119 -- IEEE; 1998 (pages 1108-1119) -- 2006

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Design Techniques for Single-Low-V~D~D CMOS Systems

Wang, J.-S. et al.

IEEE journal of solid-state circuits. VOL 40; NUMB 5, ; 2005, 1157-1165 -- IEEE; 1998 (pages 1157-1165) -- 2005

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5
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A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

Lin, C.-C. et al.

IEEE journal of solid-state circuits.; International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2007, 170-182 -- IEEE,; 2007 Part: Part 1; (pages 170-182) -- 2007

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6
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A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

Lin, C.-C. et al.

IEEE journal of solid-state circuits. VOL 42; NUMB 1, ; 2007, 170-182 -- IEEE; 1998 (pages 170-182) -- 2007

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7
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A 12-Bit 20-Msample/s Pipelined Analog-to-Digital Converter With Nested Digital Background Calibration

Wang, X.; Hurst, P. J.; Lewis, S. H.

IEEE journal of solid-state circuits. VOL 39; NUMB 11, ; 2004, 1799-1808 -- IEEE; 1998 (pages 1799-1808) -- 2004

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8
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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

Gupta, S. K.; Inerfield, M. A.; Wang, J.

IEEE journal of solid-state circuits. VOL 41; NUMB 12, ; 2006, 2650-2657 -- IEEE; 1998 (pages 2650-2657) -- 2006

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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

Gupta, S. K.; Inerfield, M. A.; Wang, J.

IEEE journal of solid-state circuits.; IEEE International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2006, 2650-2657 -- IEEE; 2006 (pages 2650-2657) -- 2006

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A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface

Tyhach, J. et al.

IEEE journal of solid-state circuits.; Custom integrated circuits; , 2004, 2005, 1829-1838 -- IEEE; 2005 (pages 1829-1838) -- 2005

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by this Author/Contributor:

  1. Wang, A. Z. H.
  2. Savoj, J.
  3. Natarajan, S
  4. Wang, J. S.
  5. Yeh, C.

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