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A 0.1- Formula Not Shown 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

Kang, S. et al.

IEEE journal of solid-state circuits. VOL 42; NUMB 1, ; 2007, 210-218 -- IEEE; 1998 (pages 210-218) -- 2007

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A 0.1-mum 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

Kang, S. et al.

IEEE journal of solid-state circuits.; International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2007, 210-218 -- IEEE,; 2007 Part: Part 1; (pages 210-218) -- 2007

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A 0.18-mum 3.0-V 64-Mb Nonvolatile Phase-Transition Random Access Memory (PRAM)

Cho, W. Y. et al.

IEEE journal of solid-state circuits. VOL 40; NUMB 1, ; 2005, 293-300 -- IEEE; 1998 Part: Part 1; (pages 293-300) -- 2005

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#151 Design of Bi-Directional and Multi-Channel Miniaturized Telemetry Module for Wireless Endoscopy

Park, H.-J. Nam, H. W. Song, B. S. Choi, J. L. Choi, H. C. Park, J. C. Kim, M. N. Lee, J. T. Cho, J. H.; Beebe, D.

Annual international IEEE/EMBS special topic conference on microtechnologies in medicine and biology.; Microtechnologies in medicine & biology; Madison, WI, 2002; May, 2002, 273-276 -- IEEE; 2002 (pages 273-276) -- 2002

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A 2-GHz Wide Band Low Phase Noise Voltage-Controlled Oscillator with On-Chip LC Tank

Cho, J.-K. et al.

Proceedings of the IEEE ... Custom Integrated Circuits Conference.; Custom integrated circuits conference; San Jose, CA, 2003; Sep, 2003, 559-562 -- IEEE; 2003 (pages 559-562) -- 2003

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A 2-GHz Wide Band Low Phase Noise Voltage-Controlled Oscillator with On-Chip LC Tank

Cho, J.-K. et al.

IEEE; 1999 (pages 559-562)

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20.2 The Effects of TaN Thickness and Strained Substrate on the Performance and PBTI Characteristics of Poly-Si/TaN/HfSiON MOSFETs

Cho, H.-J. et al.

Technical digest / International Electron Devices Meeting.; Electron devices; International electron devices meeting 2004; San Francisco, CA, 2004; Dec, 0, 503-506 -- IEEE; 2004 Part: Part; (pages 503-506)

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20.2 The Effects of TaN Thickness and Strained Substrate on the Performance and PBTI Characteristics of Poly-Si/TaN/HfSiON MOSFETs

Cho, H.-J. et al.

IEEE; 1998 Part: Part 2004; (pages 503-506) -- 2004

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20.5 Implementation of HfSiON Gate Dielectric for Sub-60nm DRAM Dual Gate Oxide with Recess Channel Array Transistors (RCAT) and Tungsten Gate

Park, S. G. et al.

Technical digest / International Electron Devices Meeting.; Electron devices; International electron devices meeting 2004; San Francisco, CA, 2004; Dec, 0, 515-520 -- IEEE; 2004 Part: Part; (pages 515-520)

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20.5 Implementation of HfSiON Gate Dielectric for Sub-60nm DRAM Dual Gate Oxide with Recess Channel Array Transistors (RCAT) and Tungsten Gate

Park, S. G. et al.

IEEE; 1998 Part: Part 2004; (pages 515-520) -- 2004

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by this Author/Contributor:

  1. Cho, B.-H.
  2. Cho, Y. S.
  3. Choi, B. H.
  4. Webber, S.
  5. Cho, B. J.

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