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Refined by: journal title: IEEE journal of solid-state circuits. remove creation date: 2004To2007 remove author: Wang, X. remove
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A 12-Bit 20-Msample/s Pipelined Analog-to-Digital Converter With Nested Digital Background Calibration

Wang, X.; Hurst, P. J.; Lewis, S. H.

IEEE journal of solid-state circuits. VOL 39; NUMB 11, ; 2004, 1799-1808 -- IEEE; 1998 (pages 1799-1808) -- 2004

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A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface

Tyhach, J. et al.

IEEE journal of solid-state circuits.; Custom integrated circuits; , 2004, 2005, 1829-1838 -- IEEE; 2005 (pages 1829-1838) -- 2005

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by this Author/Contributor:

  1. Wang, X
  2. Chong, Y.
  3. Lewis, S. H.
  4. Hurst, P. J.
  5. Wang, A. Z. H.

on this subject:

  1. custom integrated circuits

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