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A Low-Power Half-Delay-Line Fast Skew-Compensation Circuit

Wang, Y.-M.; Wang, J.-S.

IEEE journal of solid-state circuits. VOL 39; PART 6, ; 2004, 906-918 -- IEEE; 1998 (pages 906-918) -- 2004

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High-Speed and Low-Power Design Techniques for TCAM Macros

Wang, C.-C.; Wang, J.-S.; Yeh, C.

IEEE journal of solid-state circuits. VOL 43; NUMB 2, ; 2008, 530-540 -- IEEE; 1998 (pages 530-540) -- 2008

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Design of 3-V 300-MHz Low-Power 8-b x 8-b Pipelined Multiplier Using Pulse-Triggered TSPC Flip-Flops

Wang, J. S.; Yang, P. H.; Sheng, D.

IEEE journal of solid-state circuits. VOL 35; PART 4, ; 2000, 583-592 -- IEEE; 1998 (pages 583-592) -- 2000

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Low-Power Embedded SRAM with the Current-Mode Write Technique

Wang, J. S.; Tseng, W.; Li, H. Y.

IEEE journal of solid-state circuits. VOL 35; PART 1, ; 2000, 119-124 -- IEEE; 1998 (pages 119-124) -- 2000

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Analysis and Design of a New Race-Free Four-Phase CMOS Logic

Wu, C.-Y.; Cheng, K.-H.; Wang, J.-S.

IEEE journal of solid-state circuits. VOL 28; NUMBER 1, ; 1993, 18 -- IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS Part: Part 1; -- 1993

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An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices

Wang, C.-C. et al.

IEEE journal of solid-state circuits.; Radio frequency integrated circuits symposium; Atlanta, GA, 2008; Jun, 2009, 1571-1581 -- Institute of Electrical and Electronics Engineers; 2009 (pages 1571-1581) -- 2009

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A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop

Wang, J. S. et al.

IEEE journal of solid-state circuits. VOL 45; NUMBER 5, ; 2010, 1036-1047 -- IEEE; 1998 (pages 1036-1047) -- 2010

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An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices

Wang, C.-C. et al.

IEEE journal of solid-state circuits. VOL 44; NUMB 5, ; 2009, 1571-1581 -- IEEE; 1998 Part 5; (pages 1571-1581) -- 2009

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The CMOS Carry-Forward Adders

Huang, C.-H. et al.

IEEE journal of solid-state circuits. VOL 39; PART 2, ; 2004, 327-336 -- IEEE; 1998 (pages 327-336) -- 2004

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A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

Wang, J. S. et al.

IEEE journal of solid-state circuits. VOL 50; NUMBER 11, ; 2015, 2635-2644 -- IEEE; 1998 Part 11; (pages 2635-2644) -- 2015

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  1. Wang, J.-S.
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  4. Li, H.-Y.
  5. Wang, C.-C.

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