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New Module Generation Technique and System

Cai, Y.; Hong, X.

Bandaoti xuebao. VOL 16; NUMBER 3, ; 1995, 217 -- KEXUE CLUBANSHE Part: Part 3; -- 1995

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Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model

Jia, Y.; Cai, Y.; Hong, X.

IEICE transactions on fundamentals of electronics, communications and computer sciences. VOL 91; NUMB 12, ; 2008, 3783-3792 -- Oxford University Press (pages 3783-3792) -- 2008

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Reliable buffered clock tree routing algorithm with process variation tolerance

Cai, Y.; Xiong, Y.; Hong, X.

Science in China. Series F, Information sciences / Chinese Academy of Sciences. VOL 48; NUMB 5, ; 2005, 670-680 -- SPRINGER SCIENCE & BUSINESS MEDIA (pages 670-680) -- 2005

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ZERO SKEW CLOCK ROUTING WITH TREE TOPOLOGY CONSTRUCTION USING SIMULATED ANNEALING METHOD

Wei, X.; Cai, Y.; Hong, X.

IEEE international symposium on circuits and systems proceedings. VOL 1, ; 2005, 101-104 -- IEEE; 1999 (pages 101-104) -- 2005

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AN EFFICIENT ALGORITHM FOR BUFFERED ROUTING TREE CONSTRUCTION UNDER FIXED BUFFER LOCATIONS WITH ACCURATE DELAY MODELS

Zhang, Y.; Hong, X.; Cai, Y.

IEEE international symposium on circuits and systems proceedings. VOL 1, ; 2005, 97-100 -- IEEE; 1999 (pages 97-100) -- 2005

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Congestion-Driven Multilevel Full-Chip Routing Framework

Yao, H.; Cai, Y.; Hong, X.

Tsinghua science and technology. VOL 13; NUMBER 6, ; 2008, 843-849 -- Elsevier Science B. V., Amsterdam (pages 843-849) -- 2008

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A GLOBAL INTERCONNECT OPTIMIZATION ALGORITHM UNDER ACCURATE DELAY MODEL USING SOLUTION SPACE SMOOTHING

Cai, Y.; Wang, Y.; Hong, X.

IEEE international symposium on circuits and systems proceedings. VOL 1, ; 2005, 93-96 -- IEEE; 1999 (pages 93-96) -- 2005

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Clock Skew Scheduling Under Process Variations

Wei, X.; Cai, Y.; Hong, X.

PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN.; Quality electronic design; ISQED 2006; san Jose, Calif, 2006; Mar, 2006, 237-242 -- Los Alamitos, Calif.; IEEE Computer Society; c2006 (pages 237-242) -- 2006

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An Efficient Algorithm for Buffered Routing Tree Construction under Fixed Buffer Locations with Accurate Delay Models

Cai, Y.; Hong, X.; Zhang, Y.

Chinese journal of electronics. VOL 15; PART 3, ; 2006, 393-398 -- CHINESE INSTITUTEOF ELECTRONICS (pages 393-398) -- 2006

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A GLOBAL INTERCONNECT OPTIMIZATION ALGORITHM UNDER ACCURATE DELAY MODEL USING SOLUTION SPACE SMOOTHING

Cai, Y.; Wang, Y.; Hong, X.

IEEE international symposium on circuits and systems proceedings.; IEEE International Symposium on Circuits and Systems (ISCAS): May 23-26, 2005, International Conference Center, Kobe, Japan : conference proceedings; Kobe, Japan, 2005; May, 2005, 93-96 -- Piscataway, N.J.; IEEE; 2005 (pages 93-96) -- 2005

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