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A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop

Wang, J. S. et al.

IEEE journal of solid-state circuits. VOL 45; NUMBER 5, ; 2010, 1036-1047 -- IEEE; 1998 (pages 1036-1047) -- 2010

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12
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An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices

Wang, C.-C. et al.

IEEE journal of solid-state circuits. VOL 44; NUMB 5, ; 2009, 1571-1581 -- IEEE; 1998 Part 5; (pages 1571-1581) -- 2009

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13
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The CMOS Carry-Forward Adders

Huang, C.-H. et al.

IEEE journal of solid-state circuits. VOL 39; PART 2, ; 2004, 327-336 -- IEEE; 1998 (pages 327-336) -- 2004

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14
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A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

Wang, J. S. et al.

IEEE journal of solid-state circuits. VOL 50; NUMBER 11, ; 2015, 2635-2644 -- IEEE; 1998 Part 11; (pages 2635-2644) -- 2015

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15
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An AND-Type Match-Line Scheme for High-Performance Energy-Efficient Content Addressable Memories

Li, H.-Y. et al.

IEEE journal of solid-state circuits. VOL 41; NUMB 5, ; 2006, 1108-1119 -- IEEE; 1998 (pages 1108-1119) -- 2006

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16
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Design Techniques for Single-Low-V~D~D CMOS Systems

Wang, J.-S. et al.

IEEE journal of solid-state circuits. VOL 40; NUMB 5, ; 2005, 1157-1165 -- IEEE; 1998 (pages 1157-1165) -- 2005

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17
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Article
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A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop

Wang, J. S. et al.

IEEE journal of solid-state circuits.; Radio frequency integrated circuits; Boston, MA, 2009; Jun, 2010, 1036-1047 -- IEEE; 2010 (pages 1036-1047) -- 2010

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18
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A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

Lin, C.-C. et al.

IEEE journal of solid-state circuits.; International solid-state circuits conference; San Francisco, CA, 2006; Feb, 2007, 170-182 -- IEEE,; 2007 Part: Part 1; (pages 170-182) -- 2007

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19
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Article
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A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

Lin, C.-C. et al.

IEEE journal of solid-state circuits. VOL 42; NUMB 1, ; 2007, 170-182 -- IEEE; 1998 (pages 170-182) -- 2007

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20
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Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency

Lee, Y. H. et al.

IEEE journal of solid-state circuits. VOL 46; NUMBER 4, ; 2011, 904-915 -- IEEE; 1998 -- 2011

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  1. Wang, A. Z. H.
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